Below mentioned is the code for the 32-bit logic unit with the below showed logic function in the diagram. I am not sure where I am going wrong. I tried making changes in the logic function of the selection bit ‘s’ but it doesn’t seem to works somehow. module ALU_unit(output out, input x, input y, […]

- Tags "ns":0, "x3"], "x5"), "y":"13"}, "y":"14"}, "y":"24"}, {"x":"7", {"x":"9", {x:12, #input y, Below mentioned is the code for the 32-bit logic unit with the below showed logic function in the diagram. I am not sure where I am going wro, input [1:0] s); wire ns0, input x, ns1; wire w0, ns1); and (w1, ns1); and (w2, out); x = 32'd111; y = 32'd222; #1 s= 2'b00; #1 s= 2'b01; #1 s= 2'b10; #1 s= 2'b11; end endmodule Below is the image of the logic unit, output is %d \n\n", s[0]); ALU_unit m1(out[1], s[0]); not (ns1, s[1]); ALU_unit m2(out[2], s[1]); and (w0, s[1]); and (w3, s[1]); or (out, s[10]); ALU_unit m11(out[11], s[11]); ALU_unit m12(out[12], s[12]); ALU_unit m13(out[13], s[13]); ALU_unit m14(out[14], s[14]); ALU_unit m15(out[15], s[15]); ALU_unit m16(out[16], s[16]); ALU_unit m17(out[17], s[17]); ALU_unit m18(out[18], s[18]); ALU_unit m19(out[19], s[19]); ALU_unit m20(out[20], s[2]); ALU_unit m3(out[3], s[20]); ALU_unit m21(out[21], s[21]); ALU_unit m22(out[22], s[22]); ALU_unit m23(out[23], s[23]); ALU_unit m24(out[24], s[24]); ALU_unit m25(out[25], s[25]); ALU_unit m26(out[26], s[26]); ALU_unit m27(out[27], s[27]); ALU_unit m28(out[28], s[28]); ALU_unit m29(out[29], s[29]); ALU_unit m30(out[30], s[3]); ALU_unit m4(out[4], s[30]); ALU_unit m31(out[31], s[31]); initial begin $monitor("Input is %d %d, s[4]); ALU_unit m5(out[5], s[5]); ALU_unit m6(out[6], s[6]); ALU_unit m7(out[7], s[7]); ALU_unit m8(out[8], s[8]); ALU_unit m9(out[9], s[9]); ALU_unit m10(out[10], S0, t=1, t2, T3, T4, t4; and (t1, the error and above mentioned is the code in gate-level Verilog., w0, w1, w2, w3; wire t1, w3); endmodule module stimulus; reg [31:0] x, X, x^4, x0, x1, x1':[1, x10, x13, x14, x15, x16, x17, x18, x19, x2, x2:1, x20, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31, x6, x8, y, y; reg [1:0] s; wire [31:0] out; ALU_unit m0(out[0], y:[3, y:20, y:30}, y(9, y); nor (t4, y); not (ns0, y); or (t2, y); xor (t3, y)=(18, y[16], y[25], y[26], y[28], y[29], y='7%', y=0), y1, y10, y11, y12, Y15, Y17, Y19, y2", y2='7%', y21, y22, Y23, y31, y4, y5, y6, y8