According to the specifications the 3rd generation Ryzen processors have a total of 24 PCI Express v4.0 lanes from which 20 can be wired by the motherboard manufacturer in any way they choose.
For context let us assume a motherboard in which there are two PCI Express x16 connectors and a single M.2 connector. If only one of the x16 slots is populated it will communicate using all 16 lanes. If both x16 slots are populated then they both communicate using 8 lanes. The M.2 slot uses the remaining 4 lanes in all cases.
I am curious to know how exactly do the different components connected to the processor’s lanes negotiate the number of lanes being used by a single device, and how do they decide which version of the protocol is being used if the devices connected to the bus support different PCIe protocol versions, say v3.0 and v4.0? Who or what decides which version of the protocol is appropriate, or can the devices use different versions of the protocol at the same time?